1. Field of the Invention
The present invention relates to a test apparatus configured to test a device under test, and particularly to a power supply circuit for the test apparatus.
2. Description of the Related Art
In a testing operation for a semiconductor integrated circuit (which will be referred to as the “DUT” hereafter) that employs CMOS (Complementary Metal Oxide Semiconductor) technology such as a CPU (Central Processing Unit), DSP (Digital Signal Processor), memory, or the like, electric current flows in a flip-flop or a latch included in the DUT while it operates receiving the supply of a clock. When the clock is stopped, the circuit enters a static state in which the amount of current decreases. Accordingly, the sum total of the operating current (load current) of the DUT changes over time depending on the content of the test operation, and so forth.
A power supply circuit configured to supply electric power to such a DUT has a configuration employing a regulator, for example. Ideally, such a power supply circuit is capable of supplying constant electric power regardless of the load current. However, in actuality, such a power supply circuit has an output impedance that is not negligible. Furthermore, between the power supply circuit and the DUT, there is an impedance component that is not negligible. Accordingly, the power supply voltage fluctuates due to fluctuation in the load.
Fluctuation in the power supply voltage seriously affects the test margin for the DUT. Furthermore, such fluctuation in the power supply voltage affects the operations of other circuit blocks included in the test apparatus, such as a pattern generator configured to generate a pattern to be supplied to the DUT, a timing generator configured to control the pattern transition timing, etc., leading to deterioration in the test accuracy.
With such a technique described in Patent document 2, a power supply apparatus includes a compensation circuit including a switch configured such that its switching on/off is controlled according to the output of a driver, in addition to a main power supply configured to supply power supply voltage to a device under test.
FIG. 1 is a block diagram showing a configuration of a power supply apparatus including a compensation circuit investigated by the present inventors. A DUT 1 is arranged such that a power supply voltage VDD is supplied to a power supply terminal P1 thereof, and a ground terminal P2 thereof is grounded. Furthermore, a test pattern STEST is supplied to an I/O terminal P3 of the DUT 1 from a driver included in an unshown test apparatus.
A power supply apparatus 8 includes a main power supply 10 and a power supply compensation circuit 12, and is configured to supply the power supply voltage VDD to the power supply terminal P1 of the DUT 1. The output terminal of the main power supply 10 is connected to the power supply terminal P1 of the DUT 1 via a power supply line. The main power supply 10 is configured as a combination circuit composed of a digital circuit and a digital/analog converter, a linear regulator, a switching regulator, or the like. The main power supply 10 is configured to receive a feedback signal that corresponds to the power supply voltage VDD at the power supply terminal P1, and to feedback control the output voltage VOUT such that the power supply voltage VDD matches a target voltage VREF.
A source current source 12b included in the power supply compensation circuit 12 is configured to perform a switching operation according to a control pattern SCNT1, and to inject a pulse-shaped compensation current ISRC (functions as a source) into the power supply terminal P1 of the DUT 1 via a path that differs from that of the main power supply 10. A sink current source 12c is configured to perform a switching operation according to a control pattern SCNT2, and to draw a pulse-shaped compensation current ISINK (functions as a sink) via a path that differs from that of the DUT 1.
With such an arrangement, the compensation control patterns SCNT1 and SCNT2 to be applied to the power supply compensation circuit 12 are defined such that they are associated with the test pattern STEST, so as to cancel out changes in the power supply voltage VDD that occur according to the supply of the test pattern STEST to the DUT. In an actual test operation, by controlling the power supply compensation circuit 12 according to the control patterns SCNT1 and SCNT2 while supplying the test pattern STEST to the DUT 1, such an arrangement allows the power supply voltage VDD to be maintained at a constant voltage.